This section is intended to provide information relevant to understanding various technologies described herein. As the section's title implies, this is a discussion of related art that should in no way imply that it is prior art. Generally, related art may or may not be considered prior art. It should therefore be understood that any statement in this section should be read in this light, and not as any admission of prior art.
Generally, electronic designers employ various techniques to design integrated circuits, such as physical chips and/or physical layers. In some situations, during design processes, the designers may identify considerable power, performance, and area (PPA) gaps to close. Sometimes, the designers may resort to brute force manual techniques of sizing cells or ECO Routings (Engineering Change Order Routing) for closing these PPA gaps. These conventional techniques may be inefficient and cumbersome due to being approached manually. Further, in some cases, these conventional techniques may not be based on analytic data and so may be ineffective and insufficient.